Amplifiers are widely used in many electronic devices to increase the input signal level to a desired output level. A class D amplifier includes an active device used as an on-off switch, and output power variations are achieved by pulse-width modulation. Class D amplifiers may be used in radio broadcast transmitters, and audio amplifiers, for example. The very high switching efficiency of power metal-oxide field-effect transistors (MOSFETs), for example, permits their use in class D audio amplifiers to produce high fidelity signals with relatively compact and efficient circuits.
A typical digital input class D amplifier 10 is shown in FIG. 1. The amplifier 10 includes a digital format converter 11 which receives the input signal in a standard format. A sample rate converter 12 converts the output of the digital format converter for input to the pulse code modulation (PCM) to pulse width modulation (PWM) converter 13. The output of the PCM to PWM converter 13 is coupled to the illustrated level shifter 14, bridge 15, and ultimately to a transducer 16, such as a loudspeaker, for example. Reference number 17 illustrates various possible feedback paths for the amplifier 10.
Unfortunately, a significant difficulty occurs in converting the high resolution PCM signal to a corresponding high resolution PWM signal. This is so because as the width of a pulse increases, it's direct current (dc) content increases with a one-to-one relationship. Each individual pulse has a sinc(x) frequency response. If the pulse repetition rate is high enough, then the low pass filter essentially only 15 passes the dc component of each pulse and smooths the transition from one dc level to another as the dc values change as a function of time. Because this system is a sampled time system, the pulse widths are quantized in time as shown in the graphical plots of FIG. 2, where P1-P5 are the illustrated pulses, and the upper plot 18 illustrates the pulse resolution clock edges. This PWM width quantization translates directly into a dc amplitude quantization. There is a practical limitation on the pulse resolution clock 18, the clock that defines the pulse width quantization. This places an inherent limitation on the pulse width resolution which, in turn, limits the total harmonic distortion (THD) of the output signal.
For example, assuming a pulse repetition of 350 KHz, this repetition rate is high enough to support the operating assumption that the low pass filter at the amplifier's output is passing only the near dc signal component, while not being so high as to force a prohibitively high pulse resolution clock for lower resolutions. Higher resolutions are quite different. For example, if it is desired to preserve 16 bits of accuracy through the PCM to PWM conversion, then the pulse repetition clock rate required is 350 KHz times 2.sup.16 or 23 GHz. Such a high required clock rate is impractical.
One prior art approach to overcome this difficulty is to add a noise shaper or filter 21 to the processing chain upstream of the PCM to PWM converter 13 in the circuit 20 as shown in FIG. 3. The noise shaper 21 reduces the required resolution of the PCM signal, and, thus reduces the required time resolution of the subsequent PWM signal. The noise shaper 21 does this by weighting the quantization noise toward the ultimately rejected higher frequencies, and uses the high frequency noise to dither the signal of interest through the low resolution PCM to PWM converter 13. The input signal has an N bit resolution and the output signal has an M bit resolution, where N is greater than M. The ability of the noise shaper 21 to shape the noise is based upon the fact that adjacent input samples are highly correlated. This correlation is assured by the preceding interpolation in the sample rate conversion block 12.
The output signal-to-noise ratio (SNR) can be increased by increasing the degree of oversampling of the input signal, or increasing the order of the noise shaping filter 21. Unfortunately, increasing the degree of oversampling drastically increases overall system complexity, while increasing the noise shaping filter's order beyond three offers diminishing improvement in performance at reasonable oversampling rates. One source of increased system complexity occurs because interpolation filter complexity must be increased.
Another difficulty arises because increasing he oversampling increases the PWM repetition rate. Thus, to keep the same pulse resolution clock rate, one less bit is allowed in the quantizer for every factor of two that the sampling rate is increased. This may mean that for a third order noise shaping filter, a net noise floor gain of approximately 1.6 bits is realized for every factor of two that the sampling rate is increased, and assuming ideal interpolation.
Yet another difficulty with a conventional noise shaping filter 21 is based upon the dithering 10 noise that must be carried through the PCM to PWM converter 13 to decrease the required PWM timer resolution. This dithering may be later removed by the low pass filter 22. However, there may be perceptible effects in sound quality that result from the dithering.